All integrated circuit ("I.C.") devices are sensitive to ESD to some degree. However, as I.C. devices are made smaller, ESD damage is more likely to occur and render the device inoperable in response to an ESD event. Particularly susceptible are MOS and CMOS devices with thin gate oxides.
ESD results when electrostatic charge is collected and then rapidly discharged in a short duration, high voltage pulse. It has been shown that voltage potentials up to 28 kV can be generated and discharged in less than 10 nanosecond through an I.C. device when handled by a person. Electrostatic charge can also be accumulated on pin of the lead frame of a packaged I.C. device during shipping, storage or while being integrated into an electronic system which is discharged when another pin is grounded. The discharge of the high electrostatic voltage can result in a current of about two amperes. The high current must flow through the I.C. device when another pin or pad is grounded. MOS devices are particularly susceptible to discharge of the electrostatic charge because the thin gate oxide can be easily ruptured by the voltage induced by the high current.
The need for ESD protection in I.C. devices that can handle the high current produced by an ESD event has been recognized for many years. However, it is typical that ESD protection circuits are designed to provide protection against electrostatic charge levels of between 500 volts to 3.0 kilovolts because once the I.C. device has been inserted into a system, the need for ESD protection is minimized since most such systems generally incorporate sophisticated ESD protection. However, prior to insertion, I.C. devices are particularly vulnerable to ESD pulses applied to the I.C. device's pins or pads.
In a typical CMOS I.C. device, a supply voltage bus or ring, herein called the VCC ring, and a ground voltage bus or ring, herein called the VCC ring, are routed around the perimeter of the I.C. device. In some I.C. devices, the rings are concentric with one ring within the other although it is possible that the VCC ring is on a different conductive layer than the VSS ring.
One prior art protection scheme provides sufficient ESD protection to dissipate the electrostatic charge typically accumulated by a person which is typically about 2.0 kilovolts (often referred to as the human body model or "HBM"). HBM protection is achieved by placing standard size (W/L.about.150 .mu.m/2 .mu.m) N-channel or P-channel output drivers between every input and output ("I/O") pad and VSS or VCC rings, respectively. On input pads, the gate of each driver is resistively tied to the appropriate body of the semiconductor die.
To discharge accumulated charge between either the VCC or VSS rings, the prior art protection scheme used a passive clamp which is typically a standard size N-channel MOS transistor. The gate of the clamp transistor is connected to an ESD detector which may be either passive or active. The passive detector circuit typically consists of a resistor coupling the gate to VSS. Active clamp circuits consist of digital and analog components such as amplifiers and resistors and capacitors. The drain and source of the MOS transistor are connected to the VCC and VSS rings, respectively.
In order to handle the instantaneous current created by the ESD pulse, the VCC and VSS rings are typically 50 .mu.m wide on the thickest metal layer. This protection scheme is widely used on MOS I.C. devices because the silicon area required for implementation is minimal. However, this protection scheme is effective primarily for CMOS processes with geometries greater than two microns having 400 .ANG. thick gate oxide but is not effective for CMOS processes with smaller geometries and thinner gate oxides.
A circuit schematic of the above ESD protection network is shown in FIG. 1. A pad 12 is coupled to VCC ring 18 through PNP transistor 14 and pad 16 is coupled to VSS ring 22 through NPN transistor 20. The base and collector of transistors 14 and 20 are shorted together and tied to VCC ring 18 and VSS ring 22, respectively, which causes them to function as diodes. A resistor 24 may be coupled in series between the gate of transistor 26 and pad 12.
In the illustrated embodiment, in response to an two ampere ESD pulse, transistors 14 and 20 switch to the on-state in about one nanosecond and have approximately a positive five volt forward voltage drop across the emitter-base junction. As the base of NPN transistor 20 is formed from the P substrate, which is normally tied to the lowest potential (i.e., VSS), it is an obvious design choice to couple it to the VSS ring 22. For similar reasons of efficiency to keep the PNP off during normal operation, the base of PNP transistor 14 is tied to the highest potential (i.e., VCC).
Each I/O pad 12 and 16 also has a second transistor configured as a diodes 15 and 17 coupled between the pad and power rings 18 or 22, respectively. For example, in FIG. 1, diode 15 (an NPN transistor) couples pad 12 to VSS ring 22 and during an ESD event with a positive pulse, diode 15 is reverse-biased. One major design consideration for the ESD protection circuit of FIG. 1 is to avoid forcing ESD current through a device in the reverse direction. In most CMOS processes, a reverse biased PNP transistor has reverse breakdown voltage of about 18 volts and an NPN transistor's reverse breakdown voltage is about 15 volts with a snapback to about 10 volts. In either case, if the transistors of the CMOS device use a polysilicon gate and see a drain to source voltage greater than 10 volts with a simultaneous gate to source voltage greater than 10 volts for more than 50 nanoseconds, sufficient hot carriers (i.e., carriers having an energy higher than that of majority carriers normally encountered in the same material) could be generated which would rupture the gate oxide and short the gate of one or more transistors on the I.C. device. It is well known that N-channel devices are much more susceptible to damage from the application of a high amplitude voltage across its drain and source simultaneous with the application of a high amplitude voltage across its gate and source than are P-channel devices. Thus, a drain to source. V.sub.DS, voltage greater than 10 volts with a simultaneous gate to source voltage, V.sub.GS, greater than 10 volts for more than 50 nanoseconds could easily generate sufficient hot electrons to rupture a 300 .ANG. gate oxide. Even without the simultaneous application of high amplitude V.sub.GS and V.sub.DS, the gate oxide is susceptible to rupture at approximately 17 volts. Such devices would then be inoperative or damaged to the extent that each would soon fail.
In FIG. 2, a functional schematic of the ESD protection network shown in FIG. 1 is provided. A typical ESD event at pad 12 "sees" a voltage rise over the first PNP transistor 14, modeled as a diode, a voltage rise due to the resistance of the VCC ring 18, modeled as a resistor 34, a voltage rise across clamp 32, a voltage rise across the resistance of VSS ring 22, modeled as resistor 36, and a voltage rise across NPN transistor 20 modeled as a diode. During the ESD event, the aggregate voltage rise can be greater than 17 volts which can reverse-biased diodes 15 or 17 (FIG. 1) and stress the gate oxide of the I.C. device. Since any voltage over 17 volts will exceed the reverse breakdown voltage for the NPN diodes, a current path will flow from the I/O pin through the reverse-biased diode and into either the VSS or VCC ring. Thus, the aggregate voltage caused by the ESD event can destroy the gate oxide of the reverse-biased diode.
With typical MOS processes, gate dimensions of two microns, gate oxide thickness of 400 .ANG. and no lightly doped drain (LDD) regions are common design parameters. In such designs, the gate oxide is sufficiently thick such that it will require the voltage across the circuit of FIG. 2 to see at least a 20 volt rise before the oxide will rupture. The prior art protection circuit of FIGS. 1 and 2 was more than adequate because the gate oxide rupture voltage was higher than the sum of the voltage drops across the series elements in the ESD current path.
The prior art protection schemes are sufficient to protect CMOS I.C. devices having the geometries of the typical MOS processes. However, as device geometries are scaled down, gate oxides become thinner and as LDD are now required for many applications, such I.C. devices become susceptible to ESD damage at lower voltages. To rely on the reverse biased diodes of FIGS. 1 and 2 to limit the voltage rise caused by electrostatic discharge is clearly insufficient.
The possibility of such reverse-biasing in the illustrated ESD protection circuit of FIG. 1 is known. One brute force solution to limit the voltage rise is to make each component in the ESD protection circuit larger. However, this approach uses up valuable area on the I.C., making it prohibitively expensive. Moreover, while this solution improves the forward bias component resistance at the expense of a much greater amount of surface area, it only slightly improves the reverse bias breakdown level.
In addition to the above, the circuit of FIG. 1 provides only a path to VCC for positive ESD spikes and a path to VSS for negative ESD spikes. Other paths looking at FIG. 2, must go through clamp 32 usually in the reverse direction. Since clamp 32 requires a voltage in excess of about 15 volts to conduct in the reverse bias state, such paths will degrade or damage the I.C. device. Clearly as CMOS gate oxide become thinner, it is necessary to provide additional paths from one I/O pad to another I/O pad and not just to the VCC and VSS rings.
Other known solutions to this problem have also not been fully satisfactory, leaving a need for an effective ESD protection circuit using minimum I.C. area.